1. Field of the Invention
The present invention relates to a timing generation circuit, and more particularly, it relates to a timing generation circuit to be mounted on a semiconductor memory device.
2. Description of the Related Art
FIG. 6 is a circuit diagram showing a conventional timing generation circuit.
The timing generation circuit for use in an EEPROM of an IIC interface, or the like has to be reset at all timings. For example, when eight output pulses having different timings are generated, nine binary states including a system reset state are required. Therefore, the timing generation circuit includes a binary counter of four bits in which four T-flip-flop (T-FF) circuits are connected, and a decoder circuit constituted of a logic element of four inputs. The binary counter generates eight binary states. The decoder circuit generates the eight output pulses having different timings from the eight binary states, excluding the binary state at the system reset.